International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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Volume 174 - Issue 5 |
Published: Sep 2017 |
Authors: Joao Carlos Bittencourt, Wagner Luiz De Oliveira, Ricardo Chaves |
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Joao Carlos Bittencourt, Wagner Luiz De Oliveira, Ricardo Chaves . Low-footprint CLEFIA FPGA Implementations with Full-key Expansion. International Journal of Computer Applications. 174, 5 (Sep 2017), 1-8. DOI=10.5120/ijca2017915392
@article{ 10.5120/ijca2017915392, author = { Joao Carlos Bittencourt,Wagner Luiz De Oliveira,Ricardo Chaves }, title = { Low-footprint CLEFIA FPGA Implementations with Full-key Expansion }, journal = { International Journal of Computer Applications }, year = { 2017 }, volume = { 174 }, number = { 5 }, pages = { 1-8 }, doi = { 10.5120/ijca2017915392 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2017 %A Joao Carlos Bittencourt %A Wagner Luiz De Oliveira %A Ricardo Chaves %T Low-footprint CLEFIA FPGA Implementations with Full-key Expansion%T %J International Journal of Computer Applications %V 174 %N 5 %P 1-8 %R 10.5120/ijca2017915392 %I Foundation of Computer Science (FCS), NY, USA
In this paper two compact and high throughput hardware structures are proposed allowing for the computation of the 128-bit CLEFIA encryption algorithm and its associated key expansion processes. Given the needed modification to the CLEFIA Fiestel network, herein we show that with a small area and low performance impact, the CLEFIA key expansion for 128, 192 and 256-bit key can be deployed. This is achieved by using embedded components available in modern FPGAs and with an adaptable scheduling, allowing to compute the 4 and 8 branch CLEFIA Feistel network within the same structure. The obtained experimental results on a Xilinx Virtex 5 FPGA suggest that throughputs above 1Gbps can be achieved with a resource usage of 200 Slices and 3 BRAMs, achieving a throughput/Slice efficiency metric 50% higher when compared with limited state of the art.