Research Article
Low Power Dissipation Binary to BCD Converter for Multi-Operand B/D Adder
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 166 - Issue 9 |
| Published: May 2017 |
| Authors: Anshul Sharma, Pankaj Soni |
10.5120/ijca2017914109
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Anshul Sharma, Pankaj Soni . Low Power Dissipation Binary to BCD Converter for Multi-Operand B/D Adder. International Journal of Computer Applications. 166, 9 (May 2017), 5-8. DOI=10.5120/ijca2017914109
@article{ 10.5120/ijca2017914109,
author = { Anshul Sharma,Pankaj Soni },
title = { Low Power Dissipation Binary to BCD Converter for Multi-Operand B/D Adder },
journal = { International Journal of Computer Applications },
year = { 2017 },
volume = { 166 },
number = { 9 },
pages = { 5-8 },
doi = { 10.5120/ijca2017914109 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2017
%A Anshul Sharma
%A Pankaj Soni
%T Low Power Dissipation Binary to BCD Converter for Multi-Operand B/D Adder%T
%J International Journal of Computer Applications
%V 166
%N 9
%P 5-8
%R 10.5120/ijca2017914109
%I Foundation of Computer Science (FCS), NY, USA
Abstract
The main objective to design this paper to increasing importance of commercial application , economic and Internet-based applications the decimal adder provide useful statistic in formative each adder's performance and scalability. There is a new interest in providing hardware support to handle decimal data. In this paper, a new architecture binary to BCD converter for multi-operand addition implement of binary coded decimal (BCD) operands, which is the core of high speed multi-operand adders. the proposed Simulation results show that the add-3 digit BCD adder achieves an improvement of 70 % in delay and area and it consume very less power. The 2,4,8,16-digit BCD look-ahead adder shown to achieve at least 90 % faster than the accessible ripple carry one. The coding will be written in VHDL and verified in I-Sim. After the coding the synthesis of the code was performed using Xilinx-ISE. Synthesis tool ISE 14.7.
References
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- Lin, Kuan Jen, et al. "A parallel decimal adder with carry correction during binary accumulation." New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International. IEEE, 2012.
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- Bhattacharya, Jairaj, Aman Gupta, and Anshul Singh. "A high performance binary to BCD converter for decimal multiplication." VLSI Design Automation and Test (VLSI-DAT), 2010 International Symposium on. IEEE, 2010.
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