Research Article
Design and Implementation of Low Power 32 Bit Arithmetic Logic Unit
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 166 - Issue 7 |
| Published: May 2017 |
| Authors: Nazia Khan, Pankaj Soni |
10.5120/ijca2017914062
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Nazia Khan, Pankaj Soni . Design and Implementation of Low Power 32 Bit Arithmetic Logic Unit. International Journal of Computer Applications. 166, 7 (May 2017), 14-17. DOI=10.5120/ijca2017914062
@article{ 10.5120/ijca2017914062,
author = { Nazia Khan,Pankaj Soni },
title = { Design and Implementation of Low Power 32 Bit Arithmetic Logic Unit },
journal = { International Journal of Computer Applications },
year = { 2017 },
volume = { 166 },
number = { 7 },
pages = { 14-17 },
doi = { 10.5120/ijca2017914062 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2017
%A Nazia Khan
%A Pankaj Soni
%T Design and Implementation of Low Power 32 Bit Arithmetic Logic Unit%T
%J International Journal of Computer Applications
%V 166
%N 7
%P 14-17
%R 10.5120/ijca2017914062
%I Foundation of Computer Science (FCS), NY, USA
Abstract
This paper presents the construction of 32‐bit ALU (Arithmetic Logical Unit) using VHDL. The main intention to design 32 bit ALU to defeat the area and power of the design. Which is a digital circuit that executes Arithmetic Logic Unit. ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The coding will be written in VHDL and verified in I-Sim. After the coding the synthesis of the code was performed using Xilinx-ISE. Synthesis tool ISE 14.7. The ALU executes the desired operation and generates the result consequently. This designed put away very less area and only 193 LUTs occupy out of 10944 LUTs.
References
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