Abstract

In this paper, some techniques to enhance the performance of the tunneling field effect transistor (TFET) devices are studied. Two proposed techniques, which could be used simultaneously to improve the performance of TFET, are presented. The first technique is using different oxide materials for the spacers over the drain and source. The second technique is to select a different material of the source other than Si. The study is based on the DC ID-VGS characteristics as well as the high frequency characteristics regarding the capacitance and cut-off frequency. It was found from this study, that it is advantageous to use different materials for the spacers. The materials chosen for this work are HfO2 as the spacer over the source and SiO2 over the drain. It is also shown that using Ge as a source material provides the best performance. The criterion of the choices presented in this paper is based on providing higher ON current and lower ambipolar current and higher cut-off frequency.

References

• Sakurai T., “Perspectives of low power VLSI’s,” IEICE Trans. Electron, E87-C, pp. 429–436, IEICE, 2004.
• A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329–337, Nov. 2011.
• Sze, S. M., Physics of Semiconductor Devices, 1st edn (John Wiley), 1969.
• Lundstrom, M. S., “The MOSFET revisited: device physics and modeling at the nanoscale,” Proc. IEEE Int. SOI Conf. 1–3, IEEE, 2006.
• Boucart, K. & Ionescu, A. M., “Length scaling of the double gate tunnel FET with a high-κ gate dielectric,” Solid State Electron. 51, pp. 1500–1507, 2007.
• Seabaugh, A. C.; Zhang, Q., “Low-Voltage Tunnel Transistors for Beyond CMOS Logic,” Proceedings of the IEEE 98 (12): pp. 2095–2110, (2010)
• S. O. Koswatta, M. S. Lundstrom, and D. E. Nikonov, “Performance comparison between p-i-n tunneling transistors and conventional MOSFETs,” IEEE Trans. Electron Devices, vol. 56, no. 3, pp. 456–465, Mar. 2007.
• S. Saurabh and M. J. Kumar, “Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor (TFET): Theoretical investigation and analysis,” Jpn. J. Appl. Phys., vol. 48, Article ID 064503, Jun. 2009.
• R. Vishnoi and M. J. Kumar, "A Pseudo 2D-analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET," IEEE Trans. Electron Devices, Vol.61, pp. 2264-2270, July 2014.
• D. B. Abdi and M. J. Kumar, “In-built N+ pocket p-n-p-n tunnel field effect transistor", IEEE Electron Device Lett., Vol.35, No.12, pp. 1170- 1172, December 2014.
• T. Krishnamohan, D. Kim, S. Raghunathan, and K. C. Saraswat, “Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and <60 mV/dec subthreshold slope,” in Proc. IEDM Tech. Dig., San Francisco, CA, USA, pp. 947–949, 2008.
• A. Hraziia, A. Gupta, A. Vladimirescu, A. Amara, and C. Anghel, “30- nm Tunnel FET with improved performance and reduced ambipolar current,”, IEEE Trans. Electron Devices, vol. 58, pp. 1649–1654, Jun. 2011.
• J. Wana, C. L. Royer, A. Zaslavsky, S. Cristoloveanu,”Tunneling FETs on SOI: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling”, Solid-State Electron., vol. 65, pp. 226-233, Nov. 2011.
• D. B. Abdi and M. J. Kumar, “Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain,” IEEE J. Electron Devices Soc., vol. 2, no. 6, pp. 187–190, Nov. 2014.
• Shubham Sahay and M. Jagadesh Kumar, “Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using hetero-dielectric box,” IEEE Transactions on Electron Devices, Vol.62, no.11, pp.3882 - 3886, November 2015.
• ATLAS Device Simulation Software, Silvaco, Santa Clara, CA, USA, 2015.
• W. G. Vandenberghe et al., “Analytical Model for a Tunnel Field-Effect Transistor,” MELECON - The 14th IEEE Mediterranean Electrotechnical Conference, pp. 923 – 928, 2008.
• Rajat Vishnoi and M. Jagadesh Kumar, "A Pseudo 2D-analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET", IEEE Trans. on Electron Devices, Vol.61, pp.2264-2270, July 2014.
• J. Wan, C. L. Royer, A. Zaslavsky and S. Cristoloveanu, "A tunnelling field effect transistor model combining interband tunneling with channel transport", J. Appl. Phys., Vol. 110, No. 10, pp. 104503 - 104503–7, 2011.