Abstract

XOR gate forms an indispensable component in the design of code converters. The paramount concern in the design of code converters is power dissipation along with issues in delay and layout area. Various topologies to design code converters and several techniques for designing XOR gate are analyzed. GDI approach tends to provide the optimized conditions. The methodology then is applied to the conventional Binary code to Gray code converter and Gray code to Binary code converter. In this paper conventional code converters are analyzed and then a hybrid architecture for obtaining high speed, lower area, reduced power dissipation and lower propagation delay is presented. In addition to this an architecture of BCD to Excess-3 code conversion is also presented. The circuits are schematized using a Dsch tool. The layout and analysis is done through BSIM simulator and Microwind 3.1 tool.

References

• N.Weste, K.Eshraghian, “Principles of CMOS DigitalDesign”, Addison-Wesley, pp. 304-307.
• A.P. Chandrakasan, R.W. Brodersen, “Minizing Power Consumption in Digital CMOS Circuits”, Proceedings of the IEEE, vol. 83, no.4, pp. 498-523, April 1995.
• Arkadiy Morgenshtein, Viacheslav Yuzhaninov, AlexeyKovshilovsky and Alexander Fish, “Full-Swing Gate Diffusion Input Logic- Case study of low-power CLA adder design”, Integration, the VLSI journal 47 (2014) 62-70.
• R. Zimmermann and W. Fichtner, “Low power logicstyles: CMOS versus pass transistor logic”, IEEE J. Solid–State circuits, vol. 32, pp. 1079-1090, June 1997.
• V. Adler, E. G. Friedman, “Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load”, Analog Integrated Circuit and Signal Processing, 14, 1997, pp. 29-39.
• T. Sakurai, “Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI’s”, IEEE Transactions on Electron Devices, vol. 40, no. 1, pp. 118-124, January 1993.
• K. Yano, Y. Sasaki, K. Rikino, K. Seki, “Top-Down Pass Transistor Logic Design”, IEEE Journal of Solid-State Circuits, vol. 31, no. 6, pp. 792-803, June 1996.
• Arkadiy Morgenshtein, A. Fish and I. A. Wagner, “ Gate Diffusion Input (GDI) – a power- efficient method for digital combinatorial circuits”, IEEE Transactions on VLSI Systems 10 (5) (2002).
• Arkadiy Morgenshtein, Idan Shwartz and Alexander Fish, “Gate Diffusion Input (GDI) Logic in standard CMOS Nanoscale process”, IEEE 26th Convention of Electrical and Electronics Engineers, Israel, 2010.
• K. Roy, S. Mukhopadhyay, H. Mahmoodi- Meimand, “Leakage Current Mechanism and Leakage Reduction Techniques in Deep Submicrometer CMOS circuits”, proceedings of the IEEE, vol. 91, no. 2, Feb 2003.
• Adel S. Sedra and Kenneth C. Smith, “Microelectronic Circuits Theoy and Applications”, Oxford Publication fifth ed. 2004.
• Shiv Shankar Mishra, Adarsh Kumar Agrawal and R. K. Nagaria, “A comparative performance analysis of various CMOS design techniques for XOR and XNOR circuits”, IJET 1(1): 1-10 (2010).
• Sung-Mo Kang, Yusuf Lablebici, “CMOS Digital integrated Circuits: Analysis and Design”, 3rd edition Tata Mc-Graw Hill, 2003.
• Laxmi Kumre, Ajay Somkuwar and Ganga Agnihotri, “ Analysis of GDI Technique for digital circuit design”, International Journal of Computer Application, vo. 76, no. 16, Aug 2013.
• R. J. Baker, Harry W. Li and David E. Boyce, “ CMOS circuit design , layout and simulation”, IEEE Press Series.
• Simran Kaur, Balwinder Singh and D. K. Jain, “Design and performance of various adders and multipliers using GDI Technique”, International Journal of VLSI design and communication (VLSICS), vol.6, no.5, Oct 2015.
• Ajay Kumar Dadoria and Kavita Khare, “A Novel approach for leakage power reduction in 65nm technologies”, International Journal of VLSI design and communication (VLSICS), vol.5, no.3, June 2014.