Research Article
Transistor Gating Technique: Designing of Full Subtractor Circuit Implementing Sleepy Transistors in 45 nm Technology
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 143 - Issue 5 |
| Published: Jun 2016 |
| Authors: Tanvi Nagariya, Braj Bihari Soni |
10.5120/ijca2016910207
|
Tanvi Nagariya, Braj Bihari Soni . Transistor Gating Technique: Designing of Full Subtractor Circuit Implementing Sleepy Transistors in 45 nm Technology. International Journal of Computer Applications. 143, 5 (Jun 2016), 40-45. DOI=10.5120/ijca2016910207
@article{ 10.5120/ijca2016910207,
author = { Tanvi Nagariya,Braj Bihari Soni },
title = { Transistor Gating Technique: Designing of Full Subtractor Circuit Implementing Sleepy Transistors in 45 nm Technology },
journal = { International Journal of Computer Applications },
year = { 2016 },
volume = { 143 },
number = { 5 },
pages = { 40-45 },
doi = { 10.5120/ijca2016910207 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2016
%A Tanvi Nagariya
%A Braj Bihari Soni
%T Transistor Gating Technique: Designing of Full Subtractor Circuit Implementing Sleepy Transistors in 45 nm Technology%T
%J International Journal of Computer Applications
%V 143
%N 5
%P 40-45
%R 10.5120/ijca2016910207
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Full subtractor is a combinational circuit that performs subtraction between the three inputs and provides result in difference and borrow outputs. Implementing the MTCMOS technique on this circuit results in reduction of leakage current and power consumption. The proposed Full Subtractor has been designed and simulated using DSCH 3.1 and MICROWIND 3.1 software. The simulation technology used is 45 nm. The simulation level is BSIM advanced level. The proposed design power consumption calculated as 0.341 mW and maximum current Idd max equal to 2.420 mA at 0.7 Supply voltages.
References
- Gautam M., Akashe S., “Transistor gating: reduction of leakage current and power in full subtractor circuit.” Advance Computing Conference (IACC), 2013,pp 1514-1517.
- Basha MM., Dr.Ramanaiah KV, Dr.Reddy PR, “Novel energy efficient 1-bit full subtractor at 65nm technology” Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015.
- Gautam M., Akashe S., “Reduction of leakage current and power in full subtractor using MTCMOS technique” Computer Communication and Informatics (ICCCI), 2013.
- Krishna S., Raghu MC and Faris S., “An efficient design of full Subtractor cell and its application in ripple borrow subtractor” International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 4, Issue 5, May 2015, pp 1473-1476.
- Saroja MD, Naik MR, “Reduction of leakage current and power in full subtractor using MTCMOS technique” International Journal of Review in Electronics and Communication Engineering IJRECE (2014) Vol2, Issue 4, August 2014.
- Rawat N., Jain R. “Power reduction approach in combinational circuit (Half and full subtractor)” International Journal of Science and Research (IJSR) Volume 3, Issue 7, July 2014.
- Sandana K., Sujitha K., “Static power dissipation reduction on full subtractor using MTCMOS” International Journal of Engineering & Science Research IJESR, July 2014, Vol-4, Issue-7,425-430.
- Sood T., Mehra R., “Design a Low Power Half-Subtractor Using .90µm CMOS Technology” IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 2, Issue 3 (May. – Jun. 2013), PP 51-56.
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