Abstract

Network on Chips are a method of interconnecting Processing Elements, such as processors and communication controllers, through a high scalability interconnect architecture. Planning and implementing NoCs is a complex task, and simulating them at the RTL level is time consuming which has motivated the implementation of a big number of cycle accurate and behavioral simulators. In this paper, we join the effort of NoC simulation platform implementation and we introduce a high level NoC simulation platform that is based on Mathworks Simulink and the SimEvents discrete event simulation engine. We, then, model a 2D and a 3D mesh NoCs using this method and we evaluate their performances. The obtained results are, then, validated using the booksim2 cycle accurate NoC simulator.

References

• Partha Pratim Pande, Cristian Grecu, Michael Jones, Andre Ivanov, and Resve Saleh. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. Computers, IEEE Transactions on, 54(8):1025–1040, 2005.
• Graham Schelle and Dirk Grunwald. Onchip interconnect exploration for multicore processors utilizing fpgas. In 2nd Workshop on Architecture Research using FPGA Platforms, 2006.
• Andrew B Kahng, Bin Li, Li-Shiuan Peh, and Kambiz Samadi. Orion 2.0: a fast and accurate noc power and area model for early-stage design space exploration. In Proceedings of the conference on Design, Automation and Test in Europe, pages 423–428. European Design and Automation Association, 2009.
• Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, Pengju Ren, Omer Khan, and Srinivas Devadas. Darsim: a parallel cyclelevel noc simulator. In MoBS 2010-Sixth Annual Workshop on Modeling, Benchmarking and Simulation, 2010.
• Nan Jiang, Daniel U Becker, George Michelogiannakis, James Balfour, Brian Towles, David E Shaw, John Kim, and William J Dally. A detailed and flexible cycle-accurate network-on-chip simulator. In Performance Analysis of Systems and Software (ISPASS), 2013 IEEE International Symposium on, pages 86–96. IEEE, 2013.
• Ruqaiya Al-Badi, Maha Al-Riyami, and Nasser Alzeidi. A parameterized noc simulator using omnet++. In Ultra Modern Telecommunications & Workshops, 2009. ICUMT’09. International Conference on, pages 1–7. IEEE, 2009.
• Dhiman Ghosh, Prasun Ghosal, and Saraju P Mohanty. A highly parameterizable simulator for performance analysis of noc architectures. In Information Technology (ICIT), 2014 International Conference on, pages 311–315. IEEE, 2014.
• Holger Blume, Thorsten von Sydow, Daniel Becker, and Tobias G Noll. Application of deterministic and stochastic petrinets for performance modeling of noc architectures. Journal of Systems Architecture, 53(8):466–476, 2007.
• J. Silveira, P.C. Cortez, G. Cordeiro Barroso, and C. Marcon. Employing a timed colored petri net to accomplish an accurate model for network-on-chip performance evaluation. In Quality Electronic Design (ISQED), 2014 15th International Symposium on, pages 55–59, March 2014.
• Kris Heid, Haoyuan Ying, Christian Hochberger, and Klaus Hofmann. Latest: Latency estimation and high speed evaluation for wormhole switched networks-on-chip. In Reconfigurable and Communication-Centric Systems-on-Chip (Re- CoSoC), 2014 9th International Symposium on, pages 1–7. IEEE, 2014.
• George S Fishman. Principles of discrete event simulation.[ book review]. 1978.
• Vijay S Pai, Parthasarathy Ranganathan, and Sarita V Adve. Rsim: An execution-driven simulator for ilp-based sharedmemory multiprocessors and uniprocessors. In Proceedings of the Third Workshop on Computer Architecture Education, volume 178. Citeseer, 1997.
• Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, and Avinoam Kolodny. Nocs simulation framework for omnet++. In Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, pages 265–266. ACM, 2011.
• SimEvents.
• Lionel M. Ni and Philip K. McKinley. A survey of wormhole routing techniques in direct networks. Computer, 26(2):62– 76, 1993.
• Makoto Motoyoshi. Through-silicon via (tsv). Proceedings of the IEEE, 97(1):43–48, 2009.
• Brett Feero and Partha Pratim Pande. Performance evaluation for three-dimensional networks-on-chip. In VLSI, 2007. ISVLSI’07. IEEE Computer Society Annual Symposium on, pages 305–310. IEEE, 2007.