Research Article
Innovative Low Power Transposition Memory using Double Edge Triggered Flip-flop
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 128 - Issue 4 |
| Published: October 2015 |
| Authors: P. Vamshi Bhargava, G.V. Maha Lakshmi |
10.5120/ijca2015906517
|
P. Vamshi Bhargava, G.V. Maha Lakshmi . Innovative Low Power Transposition Memory using Double Edge Triggered Flip-flop. International Journal of Computer Applications. 128, 4 (October 2015), 28-32. DOI=10.5120/ijca2015906517
@article{ 10.5120/ijca2015906517,
author = { P. Vamshi Bhargava,G.V. Maha Lakshmi },
title = { Innovative Low Power Transposition Memory using Double Edge Triggered Flip-flop },
journal = { International Journal of Computer Applications },
year = { 2015 },
volume = { 128 },
number = { 4 },
pages = { 28-32 },
doi = { 10.5120/ijca2015906517 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2015
%A P. Vamshi Bhargava
%A G.V. Maha Lakshmi
%T Innovative Low Power Transposition Memory using Double Edge Triggered Flip-flop%T
%J International Journal of Computer Applications
%V 128
%N 4
%P 28-32
%R 10.5120/ijca2015906517
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Transposition memory (TRAM) is one of the most important matrix processing block. This paper presents the design of a transposition memory implemented using 1V 45nm CMOS technology in Cadence® Virtuoso® Design Environment. A new double edge triggered flip-flop based on clock-gated pulse suppression technique is developed. This new double edge triggered flip-flop evolved from clock-gating pulse suppression technique reduces the power dissipation in the clocking system. This new clock-gated pulse suppressed double edge triggered flip-flop (CGPSDFF) is used to design the D flip-flop based architecture of a high speed TRAM and power reduction of the CGPSDFF-based TRAM is 20% better than conventional TRAM.
References
- 0.8μ 100-MHz 2-D DCT core processor,” IEEE Trans. Consumer Electronics, Vol. 40, pp. 703-710, Aug. 1994.
- T. Xanthopoulos and A. Chandrakasan, “A low-power IDCT Macro-cell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity, ” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 693-703, May 1999.
- P.H. Yang, J.S. Wang, and Y.M. Wang, “A 1GHz Low-Power Transposition Memory Using New Pulse-Clocked D Flip-Flops,” Proc. IEEE Int’l. Symp. Circuit and Systems, vol. 5, pp. 665-668, May 2000.
- W. L. Zhang, W. L. Goh, K. S. Yeo and G. H. Lim, “A novel static dual edge-trigger flip-flop for high-frequency low-power application”, Proc. IEEE Int. Symp.- Integrated Circuits 2007 pp. 208-211.
- J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V.De, “Comparative delay and energy of single edge-triggered and dual edge triggered pulsed flip-flops for high-performance microprocessors,” in Proc. ISPLED, pp. 207–212, 2001.
- S. S. Salankar and J. Shinde, “Clock gating – A power optimizing technique for VLSI circuits,” IEEE India Conf., Annual IEEE, pp. 1-4, 2011.
- W. H. Robinson, X. Wang, “A low-power double edge-triggered flip-flop with transmission gates and clock-gating,” Proc. MWSCAS, pp. 205-208, 2010.
- P. Zhao, T. Darwish, and M. Bayoumi, “High-performance and low power conditional discharge flip-flop,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 477–484, May 2004.
- G. Gerosa, “A 2.2 W, 80 MHz superscalar RISC microprocessor,” IEEE Journal Solid-State Circuits, vol. 29, no. 12, pp. 1440-1454, Dec. 1994.
- A U. Ko and P. Balsara, “High-performance energy-efficient D-flip-flop circuits,” IEEE Trans. Very Large Scale Integra. (VLSI) Systems, vol. 8, no.1, pp. 94-98, Feb. 2000.
- J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 62-70, Feb. 1989.
- B. Nikolic, V. G. Oklobzija, V. Stojanovic, W. Jia, J. K. Chiu, M. M. Leung, “Improved sense-amplifier-based flip-flop: Design and measurements,” IEEE Journal Solid-State Circuits, vol. 35, no. 6, pp. 876-883, Jun. 2000.
- S. D. Naffziger, G. Colon-Bonet, T. Fischer, R. Riedlinger, T. J.Sullivan, T. Grutkowski, “The implementation of the Itanium-2 microprocessor,” IEEE Journal Solid-State Circuits, vol. 37, no. 11, pp.1448-1460, Nov. 2002.
- H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper, “Flow-through latch and edge-triggered flip-flop hybrid elements,” in Proc. IEEE Dig. ISSCC, pp. 138-139 1996.
- F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta, R. Heald, and G. Yee, “A new family of semidynamic and dynamic flip-flops with embedded logic for high performance processors,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 712-716, May 1999.
- W. Fichtner and R. Zimmennann, “Low power logic styles: CMOS versus pass-transistor logic,” IEEE J. Solid-state Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997.
- J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V.De, “Comparative delay and energy of single edge-triggered and dual edge triggered pulsed flip-flops for high-performance microprocessors,” in Proc. ISPLED, pp. 207–212, 2001.
- G. Mareswara Rao, S. Rajendar, "Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic", International Journal of Computer Applications, vol. 80, no. 15, pp. 9-12 Oct 2013.
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