Research Article
Implementation for Minimization of Computation Time of Partial Products for Designing Multipliers using Tabulated Vedic Mathematics
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 128 - Issue 10 |
| Published: October 2015 |
| Authors: Nashrah Fatima, Taha Tanveer, Brahmi Shrman |
10.5120/ijca2015906638
|
Nashrah Fatima, Taha Tanveer, Brahmi Shrman . Implementation for Minimization of Computation Time of Partial Products for Designing Multipliers using Tabulated Vedic Mathematics. International Journal of Computer Applications. 128, 10 (October 2015), 1-5. DOI=10.5120/ijca2015906638
@article{ 10.5120/ijca2015906638,
author = { Nashrah Fatima,Taha Tanveer,Brahmi Shrman },
title = { Implementation for Minimization of Computation Time of Partial Products for Designing Multipliers using Tabulated Vedic Mathematics },
journal = { International Journal of Computer Applications },
year = { 2015 },
volume = { 128 },
number = { 10 },
pages = { 1-5 },
doi = { 10.5120/ijca2015906638 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2015
%A Nashrah Fatima
%A Taha Tanveer
%A Brahmi Shrman
%T Implementation for Minimization of Computation Time of Partial Products for Designing Multipliers using Tabulated Vedic Mathematics%T
%J International Journal of Computer Applications
%V 128
%N 10
%P 1-5
%R 10.5120/ijca2015906638
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Multiplication is the most time consuming process in various signal processing operations like Convolution, Circular Convolution, auto-correlation, and Cross Correlation, Image processing applications such as edge detection, microprocessors arithmetic and logical units etc. The multiplier circuit uses adder logic which reduces speed of operation due to its path propagation delay. The designs used offer tradeoffs between Computational time area, latency and throughput for performing multiplication. In this paper an ancient Indian Vedic mathematics sutras base multiplier have been proposed with Urdhva Tiryakbhyam sutra. In this methodology the length of input sequence used for multiplication varies from two to eight.
References
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- Yogita Bansal, Charu Madhu, Pardeep Kaur "High Speed Vedic Multiplier Designs a Review" Proceedings of 2014 RAECS UIET Panjab University Chandigarh, pp no. 06 – 08 March, 2014.
- Diptendu Kumar Kundu1, Supriyo Srimani2, Saradindu Panda3, Prof. Bansibadan Maji4 " Implementation of Optimized High Performance 4x4 Multiplier using Ancient Vedic Sutra in 45 nm Technology" IEEE Second International Conference on Devices, Circuits and Systems (ICDCS) 2014.
- Aravind E Vijayan, Arlene John, Deepak Sen "Efficient Implementation of 8-bit Vedic Multipliers for Image Processing Application" IEEE International Conference on Contemporary Computing and Informatics (IC3I) 2014 pp no. 544-550.
- P.Mehta and D. Gawali, “Conventional versus Vedic mathematical method for Hardware implementation of a multiplier.” In Proceedings IEEE international conference on Advances in Computing, Control and Telecommunication Technologies. Trivandrum, Kerela, Dec.28-29 T 2009, pp.640-642
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