Research Article

Implementation of Complex Matrix Inversion using Gauss-Jordan Elimination Method in Verilog

by  P.Venkata Rao, K.R.K.Sastry
journal cover
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 122 - Issue 3
Published: July 2015
Authors: P.Venkata Rao, K.R.K.Sastry
10.5120/21678-4768
PDF

P.Venkata Rao, K.R.K.Sastry . Implementation of Complex Matrix Inversion using Gauss-Jordan Elimination Method in Verilog. International Journal of Computer Applications. 122, 3 (July 2015), 6-9. DOI=10.5120/21678-4768

                        @article{ 10.5120/21678-4768,
                        author  = { P.Venkata Rao,K.R.K.Sastry },
                        title   = { Implementation of Complex Matrix Inversion using Gauss-Jordan Elimination Method in Verilog },
                        journal = { International Journal of Computer Applications },
                        year    = { 2015 },
                        volume  = { 122 },
                        number  = { 3 },
                        pages   = { 6-9 },
                        doi     = { 10.5120/21678-4768 },
                        publisher = { Foundation of Computer Science (FCS), NY, USA }
                        }
                        %0 Journal Article
                        %D 2015
                        %A P.Venkata Rao
                        %A K.R.K.Sastry
                        %T Implementation of Complex Matrix Inversion using Gauss-Jordan Elimination Method in Verilog%T 
                        %J International Journal of Computer Applications
                        %V 122
                        %N 3
                        %P 6-9
                        %R 10.5120/21678-4768
                        %I Foundation of Computer Science (FCS), NY, USA
Abstract

It gives the architecture of an optimized complex matrix inversion using GAUSS-JORDAN (GJ) elimination in Verilog with single precision floating-point representation. The GJ-elimination algorithm uses a single precision floating point arithmetic components and control unit for performing necessary arithmetic operations. The proposed architecture implements the GJ-elimination algorithm for complex matrix element sequentially. Matrix inversion using GJ-elimination improves the frequency when compared with QR Decomposition algorithm. The design is targeted on XC5VLX50T Xilinx FPGA.

References
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Index Terms
Computer Science
Information Sciences
No index terms available.
Keywords

Matrix inversion Gauss-Jordan Elimination Floating Point and True Dual Port RAM

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