Research Article
Development and Verification of Iterative Decoder for LDPC-RS Product Codes
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 121 - Issue 10 |
| Published: July 2015 |
| Authors: Maruthi L N, K S Gurumurthy |
10.5120/21573-4617
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Maruthi L N, K S Gurumurthy . Development and Verification of Iterative Decoder for LDPC-RS Product Codes. International Journal of Computer Applications. 121, 10 (July 2015), 1-4. DOI=10.5120/21573-4617
@article{ 10.5120/21573-4617,
author = { Maruthi L N,K S Gurumurthy },
title = { Development and Verification of Iterative Decoder for LDPC-RS Product Codes },
journal = { International Journal of Computer Applications },
year = { 2015 },
volume = { 121 },
number = { 10 },
pages = { 1-4 },
doi = { 10.5120/21573-4617 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2015
%A Maruthi L N
%A K S Gurumurthy
%T Development and Verification of Iterative Decoder for LDPC-RS Product Codes%T
%J International Journal of Computer Applications
%V 121
%N 10
%P 1-4
%R 10.5120/21573-4617
%I Foundation of Computer Science (FCS), NY, USA
Abstract
LDPC codes provide good random error performance nearer to Shannon limit. The LDPC codes have some residue errors which cannot be corrected even after large number of iterations such errors can be corrected by concatenating LDPC codes with RS codes. This paper describes the development of an iterative decoder scheme for LDPC-RS product codes which made LDPC codes and Turbo codes popular. The iterative structure consists of a soft decision decoding of LDPC codes and hard decision decoding of RS codes. The concatenated scheme provides higher performance than the iterative decoder for LDPC codes. The iterative scheme is developed in MATLAB and FPGA kit is used for practical verification.
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