|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 120 - Issue 22 |
| Published: June 2015 |
| Authors: Namrata H. Patel, Risha A Tiwari |
10.5120/21391-4434
|
Namrata H. Patel, Risha A Tiwari . Implementation of Power Efficient Decoding Algorithm for LDPC Code. International Journal of Computer Applications. 120, 22 (June 2015), 13-17. DOI=10.5120/21391-4434
@article{ 10.5120/21391-4434,
author = { Namrata H. Patel,Risha A Tiwari },
title = { Implementation of Power Efficient Decoding Algorithm for LDPC Code },
journal = { International Journal of Computer Applications },
year = { 2015 },
volume = { 120 },
number = { 22 },
pages = { 13-17 },
doi = { 10.5120/21391-4434 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2015
%A Namrata H. Patel
%A Risha A Tiwari
%T Implementation of Power Efficient Decoding Algorithm for LDPC Code%T
%J International Journal of Computer Applications
%V 120
%N 22
%P 13-17
%R 10.5120/21391-4434
%I Foundation of Computer Science (FCS), NY, USA
Mobile computing devices like mobile, laptops& tablets that covered large market of end user facing battery issues is an open challenge for research scholars. In this project work I have attempt to optimize power [batteries relate issues] at decoding. Stare of most efficient error control LDPC code which is being used. In this work bit flipping decoder hard decision decoding is used which can be implemented by using 8 transistor by using XOR gate. This paper proposed 6 transistor XOR gate design and implemented which can be used in this decoder.