Abstract

Testing has become an important design step now days in digital circuit. A gate level fault simulation environment based on realistic fault models has been presented in this paper. A Genetic Algorithm (GA) is proposed which allows having fault simulation with conditional execution of test vector under 2 phase scheme. By using this approach a random search of test vectors is possible without being caught in a local minima or maxima. The award of fitness to the vector set allows having a selection of test vectors with high fault coverage and with large fault detection scores. Experimental results are provided which shows that the proposed technique can be employed for the detection of faults in a sequential circuit with high fault coverage.

References

• Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel, “ Sequential circuit test generation using dynamic state traversal”, Proc of European Design and Test Conference, ED&TC 97, pp 22 – 28, 1997
• Pomeranz, I. Reddy, S.M., “On maximizing the fault coverage for a given test length limit in a synchronous sequential circuit”, Proc of VLSI Test Symposium, pp 173 – 178, 2003
• Pomeranz, I. Reddy, S.M., “TOV: Sequential Test Generation by Ordering of Test Vectors”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 454 – 465, 2010
• Wen Ching Wu, Chung Len Lee, "A Two-Phase Fault Simulation Scheme for Sequential Circuits," pp.41, 10th Anniversary Compendium of Papers from Asian Test Symposium 1992-2001 (ATScomp'01), 2001
• Rudnick, E.M.; Patel, J.H.; Greenstein, G.S.; Niermann, T.M., “A genetic algorithm framework for test generation”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp 1034 – 1044, 1997
• Pomeranz, I. Reddy, S.M., “Vector replacement to improve static-test compaction for synchronous sequential circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 336 – 342, 2001
• Elizabeth M. Rudnick,Janak H. Patel,Gary S. Greenstein,Thomas M. Niermann, “Sequential circuit test generation in a genetic algorithm framework”,Proceedings of the 31st annual Design Automation Conference, pp 698-704, 1994
• E. M. Rudnick, J. G. Holm, D. G. Saab, and J. H. Patel, "Application of simple genetic algorithms to sequential circuit test generation," Proc. European Design and Test Conf., 1994, pp. 40-45.
• M. Srinivas and L. M. Patnaik, "A simulation-based test generation scheme using genetic algorithms," Proc. Int. Conf. VLSI Design, pp. 132-135, 1993
• Pomeranz, I. Reddy, S.M., “ A built-in self-test method for diagnosis of synchronous sequential circuits”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp 290 – 296, 2001
• Shuo Sheng Hsiao, M.S., “Efficient sequential test generation based on logic simulation”, IEEE Transactions On Design & Test of Computers, pp 56 – 64, 2002
• Xiaoming Yuy, Jue Wuz, Elizabeth M. Rudnicky, “Diagnostic Test Generation for Sequential Circuits”, Proc of International Test Conference 2000 (ITC'00), pp.225-234, 2000
• V.Rajesh, Ajai Jain, “ Automatic Test Pattern Generation for Sequential Circuits using Genetic Algorithm”, Proc of Eleventh International Conference on VLSI Design: VLSI for Signal Processing, pp 270-273, 1998
• Xiaoming Yu Abramovici, M., “Sequential circuit ATPG using combinational algorithms”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 1294 – 1310, 2005
• Michael S. Hsiao, Elizabeth M.Rudnick and Janak H. Patel, “Fast static compaction algorithms for sequential circuit test vectors, IEEE Transactions on Computers, pp 311 – 322, 1999
• Ruifeng Guo,Sudhakar M. Reddy ,Irith Pomeranz, “ On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits”, Proceedings of the 10th Asian Test Symposium table of contents, pp 82-87, 2001