International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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Volume 117 - Issue 6 |
Published: May 2015 |
Authors: M.Kuttimani Rajalingam, A.Muthumanicckam, R.Sornalatha |
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M.Kuttimani Rajalingam, A.Muthumanicckam, R.Sornalatha . Design and Implementation of RNS Reverse Converter using Parallel Prefix Adders. International Journal of Computer Applications. 117, 6 (May 2015), 16-20. DOI=10.5120/20558-2945
@article{ 10.5120/20558-2945, author = { M.Kuttimani Rajalingam,A.Muthumanicckam,R.Sornalatha }, title = { Design and Implementation of RNS Reverse Converter using Parallel Prefix Adders }, journal = { International Journal of Computer Applications }, year = { 2015 }, volume = { 117 }, number = { 6 }, pages = { 16-20 }, doi = { 10.5120/20558-2945 }, publisher = { Foundation of Computer Science (FCS), NY, USA } }
%0 Journal Article %D 2015 %A M.Kuttimani Rajalingam %A A.Muthumanicckam %A R.Sornalatha %T Design and Implementation of RNS Reverse Converter using Parallel Prefix Adders%T %J International Journal of Computer Applications %V 117 %N 6 %P 16-20 %R 10.5120/20558-2945 %I Foundation of Computer Science (FCS), NY, USA
The implementation of residue number system reverse converters based on well-known regular and modular parallel prefix adders is analyzed. The VLSI implementation results show a significant delay reduction and area × time2 improvements, all this at the cost of higher power consumption, which is the main reason preventing the use of parallel-prefix adders to achieve high-speed reverse converters in recent systems. Hence, to solve the high power consumption problem, novel specific hybrid parallel-prefix based adder components that provide better trade-off between delay and power consumption are herein presented to design reverse converters. We propose Parallel distributed arithmetic convolution technique in Reverse Converter to increase the system performance