Research Article
VLSI Implementation of Low Power Area Efficient Fast Carry Select Adder
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 115 - Issue 6 |
| Published: April 2015 |
| Authors: J.Eric Clapten, E.Konguvel, M.Thangamani |
10.5120/20153-2298
|
J.Eric Clapten, E.Konguvel, M.Thangamani . VLSI Implementation of Low Power Area Efficient Fast Carry Select Adder. International Journal of Computer Applications. 115, 6 (April 2015), 5-8. DOI=10.5120/20153-2298
@article{ 10.5120/20153-2298,
author = { J.Eric Clapten,E.Konguvel,M.Thangamani },
title = { VLSI Implementation of Low Power Area Efficient Fast Carry Select Adder },
journal = { International Journal of Computer Applications },
year = { 2015 },
volume = { 115 },
number = { 6 },
pages = { 5-8 },
doi = { 10.5120/20153-2298 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2015
%A J.Eric Clapten
%A E.Konguvel
%A M.Thangamani
%T VLSI Implementation of Low Power Area Efficient Fast Carry Select Adder%T
%J International Journal of Computer Applications
%V 115
%N 6
%P 5-8
%R 10.5120/20153-2298
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Carry Select Adder (CSLA) is one of the speedest adder utilized as a part of numerous computational frameworks to perform quick number-crunching operations. The Carry select adder utilizes an effective plan by imparting the Common Boolean logic (CLB) term. The modified CSLA architecture building design has created utilizing Binary to Excess-1 converter (BEC). This paper introduces an unique method that replaces the BEC using common Boolean logic. Experimental analysis illustrates that the proposed architecture achieves advantages in terms of speed, area consumption and power.
References
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