Research Article
Relative Performance Analysis of Different CMOS Full Adder Circuits
|
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
|
| Volume 114 - Issue 6 |
| Published: March 2015 |
| Authors: Madhuresh Suman, Jagannath Samanta, Dibyendu Chowdhury, Jaydeb Bhaumik |
10.5120/19981-1922
|
Madhuresh Suman, Jagannath Samanta, Dibyendu Chowdhury, Jaydeb Bhaumik . Relative Performance Analysis of Different CMOS Full Adder Circuits. International Journal of Computer Applications. 114, 6 (March 2015), 8-14. DOI=10.5120/19981-1922
@article{ 10.5120/19981-1922,
author = { Madhuresh Suman,Jagannath Samanta,Dibyendu Chowdhury,Jaydeb Bhaumik },
title = { Relative Performance Analysis of Different CMOS Full Adder Circuits },
journal = { International Journal of Computer Applications },
year = { 2015 },
volume = { 114 },
number = { 6 },
pages = { 8-14 },
doi = { 10.5120/19981-1922 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2015
%A Madhuresh Suman
%A Jagannath Samanta
%A Dibyendu Chowdhury
%A Jaydeb Bhaumik
%T Relative Performance Analysis of Different CMOS Full Adder Circuits%T
%J International Journal of Computer Applications
%V 114
%N 6
%P 8-14
%R 10.5120/19981-1922
%I Foundation of Computer Science (FCS), NY, USA
Abstract
Different adder circuits are elementary blocks in many contemporary integrated circuits, which are not only employed to perform addition operations, but also other arithmetic operations such as subtraction, multiplication and division. Full adder is the basic building block of any adder circuit. Area, speed and power are the three main design metrics for any VLSI circuit. In this work, eight different full adders' circuits based on standard (std. ) CMOS, CPL, 16-Transistor, DCVSL, PTL, TGA, 14-Transistor and 8-Transistor have been designed and implemented using Tanner EDA simulation tool. In this paper, authors have compared the propagation delay, power consumption and power delay product (PDP) of different full adder circuits by varying supply voltage (Vdd).
References
- A. Chandrakasan, R. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proc. IEEE, vol. 83, pp. 498–523, Apr. 1995.
- M. Alioto, G. Palumbo, "Analysis and Comparison on Full adder Block in Submicron Technology," IEEE transactions on VLSI Systems, Vol. 10, No. 6, p. p. 802-823, December 2002.
- M. Vesterbacka, "A 14-transistor CMOS full adder with full voltage-swing nodes", IEEE Int. conf. on signal processing system. pp: 713-722, 1999.
- K. Navi, O. Kavehie, M. Rouholamini, A. Sahafi, S. Mehrabi, "A Novel CMOS Full Adder", 20th Int. Conference on VLSI Design , pp: 303 – 307, 2007.
- Y. Sunil, G. Reddy, V. R. Prasad "Comparison of CMOS and Adiabatic Full Adder Circuits", Int. Journal of Scientific & Engineering Research, Vol. 2, Issue 9, pp:1-5, September-2011.
- J. Samanta and B. P. De, "Comprehensive analysis of delay in UDSM CMOS circuits", Int. Conf. Electronics Communication and Computing Technologies, Tamil Nadu, India, pp:29-32, 2011.
- G. S. Kishore, "A Novel Full Adder with High Speed Low Area", Int. Journal of Computer Applications (IJCA), No. 1, Article 3, pp: 34-37, 2011.
- S. Misra, S. Akashe, "Leakage Minimization of 10T Full Adder Using Deep Sub-micron Technique", 3rd Int. Conference on Advanced Computing and Commu. Technologies (ACCT), 2013, pp: 158 – 162, 2013.
- M. A. Hernandez, M. L. Aranda, "CMOS Full-Adders for Energy-Efficient Arithmetic Applications", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 4, pp: 718 – 721, 2011.
- G. Kaur, A. Kumar, J. Singh " Design of High Speed Full Adder using Improved Differential Split Logic Technique for 130nm Technology and its Implementation in making ALU", Int. Journal of Computer Applications, Vol. 96, No. 18, 2014.
- J. Samanta, A. Patra, D. Mishra, R. Rashmi, I. Kundu, R. Koley "Performance Analysis of Different Topologies of 1-Bit Full Adder in UDSM Technology", Int. Journal of Innovative Technology and Exploring Engineering, Vol. 1, Issue-2, pp:35-42, 2012.
- M. B. Damle, Dr. S. S Limaye, M. G. Sonwani, "Comparative Analysis of Different Types of Full Adder Circuits", IOSR Journal of Computer Engineering, Vol. 11, Issue 3, pp:1-9, 2013.
- R. Gupta, S. P. Pandey, S. Akashe, A. Vidyarthi, "Analysis and optimization of Active Power and Delay of 10T Full Adder using Power Gating Technique at 45 nm Technology", IOSR Journal of VLSI and Signal Processing, Vol. 2, Issue 1, pp: 51-57 2013.
- A. Kumar, A. K. Goyal, "Study of Various Full Adders using Tanner EDA Tool", Int. Journal of Computer Science And Technology, Vol. 3, Issue 1, pp:581-585, 2012.
- R. UMA, V. Vijayan, M. Mohanapriya, S. Paul, "Area, Delay and Power Comparison of Adder Topologies", Int. Journal of VLSI design & Commu. Systems, Vol. 3, No. 1, pp:153-168, 2012.
- N. Gupta, "Designing of Full Adder Circuits for Low Power", International Journal of Scientific Research Engineering & Technology (IJSRET), vol. 2 no. 4 pp. 215-219, July 2013.
Index Terms
Keywords