Research Article
Article:Reconfigurable FFT System on Chip (SOC)
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 11 - Issue 5 |
| Published: December 2010 |
| Authors: G. Venkataramana Sagar, Dr. K. Srinivasa Rao |
10.5120/1575-2107
|
G. Venkataramana Sagar, Dr. K. Srinivasa Rao . Article:Reconfigurable FFT System on Chip (SOC). International Journal of Computer Applications. 11, 5 (December 2010), 35-38. DOI=10.5120/1575-2107
@article{ 10.5120/1575-2107,
author = { G. Venkataramana Sagar,Dr. K. Srinivasa Rao },
title = { Article:Reconfigurable FFT System on Chip (SOC) },
journal = { International Journal of Computer Applications },
year = { 2010 },
volume = { 11 },
number = { 5 },
pages = { 35-38 },
doi = { 10.5120/1575-2107 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2010
%A G. Venkataramana Sagar
%A Dr. K. Srinivasa Rao
%T Article:Reconfigurable FFT System on Chip (SOC)%T
%J International Journal of Computer Applications
%V 11
%N 5
%P 35-38
%R 10.5120/1575-2107
%I Foundation of Computer Science (FCS), NY, USA
Abstract
With onset of paradigms of System On Chip (SOC) to design a module for real time applications or voice codec’s, The SOC’s have different requirements for operands precision we propose a reusable FFT [2] using reconfigurable multiplier [6]. How ever, the FFT perform either combining N and N/2 bit multiplications in the same N bit tree multiplier. The key challenges in designing a reusable FFT are to limit the impact of flexibility on power operations that are needed for FFT butterfly to perform better than a conventional, dedicated FFT butterfly.
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