Research Article
Novel 16-Bit and 32-Bit Group High Speed BCD Adders
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
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| Volume 107 - Issue 12 |
| Published: December 2014 |
| Authors: Sundaresan C, Chaitanya Cvs, Mohan Kumar J, Pr Venkateswaran, Somashekara Bhat |
10.5120/18805-0371
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Sundaresan C, Chaitanya Cvs, Mohan Kumar J, Pr Venkateswaran, Somashekara Bhat . Novel 16-Bit and 32-Bit Group High Speed BCD Adders. International Journal of Computer Applications. 107, 12 (December 2014), 36-38. DOI=10.5120/18805-0371
@article{ 10.5120/18805-0371,
author = { Sundaresan C,Chaitanya Cvs,Mohan Kumar J,Pr Venkateswaran,Somashekara Bhat },
title = { Novel 16-Bit and 32-Bit Group High Speed BCD Adders },
journal = { International Journal of Computer Applications },
year = { 2014 },
volume = { 107 },
number = { 12 },
pages = { 36-38 },
doi = { 10.5120/18805-0371 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2014
%A Sundaresan C
%A Chaitanya Cvs
%A Mohan Kumar J
%A Pr Venkateswaran
%A Somashekara Bhat
%T Novel 16-Bit and 32-Bit Group High Speed BCD Adders%T
%J International Journal of Computer Applications
%V 107
%N 12
%P 36-38
%R 10.5120/18805-0371
%I Foundation of Computer Science (FCS), NY, USA
Abstract
The VLSI binary adder is the basic building block in any computation unit. It is widely used in the arithmetic logic unit, memory addressing computation and in many other places. In this paper the binary adder is presented with keeping in mind speed, power and finally area. In this paper the BCD adder is designed using the mixed approach such as hierarchical, muxing and variable grouping techniques. The design and result are presented in this paper.
References
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