Abstract

Reversible logic is highly useful in nanotechnology, low power design and quantum computing. The paper proposes efficient MOS implementation for the basic reversible gates namely, Feynman, Toffoli, and Peres gates and employs the proposed circuits in the reversible binary multiplier design. It also juxtaposes the three proposed architectures to compare their properties and hence propose the most optimized form of the aforementioned multipliers.

References

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