The main objective of this proposed is to design to improve the error performance with high throughput and without consuming much chip area. VLSI-based decoding of geometric low-density parity-check (LDPC) codes using the sum–product or min-sum algorithms is known to be very difficult due to large memory requirement and high interconnection complexity caused by high variable and column degrees. In this paper, a low-complexity high-performance algorithm is introduced for decoding of high-weight LDPC codes. The developed soft-bit-flipping (SBF) algorithm having every advantages of bit-flipping (BF) algorithm and more advantages like further utilizes reliability of estimates to improve error performance. A hybrid decoding scheme comprised of the BF and SBF algorithms is also proposed to shorten the decoding time. Parallel and pipelined VLSI architecture is developed to increase the throughput without consuming much chip area.

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Bit flipping (BF) finite geometry low-density parity-check (LDPC) codes projective geometry (PG) soft BF (SBF)